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path: root/opcodes/i386-opc.h
Commit message (Expand)AuthorAgeFilesLines
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-0/+3
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-0/+9
* X86: Remove pcommit instructionH.J. Lu2016-10-211-3/+0
* X86: Add ptwrite instructionH.J. Lu2016-08-241-0/+3
* Update x86 CPU_XXX_FLAGS handlingH.J. Lu2016-05-271-0/+15
* Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2016-05-271-7/+7
* Correct CpuMax in i386-opc.hH.J. Lu2016-05-271-1/+1
* Enable Intel RDPID instruction.Alexander Fomin2016-05-101-0/+3
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* Implement Intel OSPKE instructionsH.J. Lu2015-12-091-0/+3
* Remove trailing spaces in opcodesH.J. Lu2015-08-121-1/+1
* Add support for monitorx/mwaitx instructionsAmit Pawar2015-06-301-0/+3
* Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu2015-05-151-0/+6
* Add Intel MCU support to opcodesH.J. Lu2015-05-111-0/+3
* Add znver1 processorGanesh Gopalasubramanian2015-03-171-0/+3
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-1/+1
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-0/+3
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-0/+3
* Add pcommit instructionIlya Tocar2014-11-171-0/+3
* Add clwb instructionIlya Tocar2014-11-171-0/+3
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-0/+3
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-0/+3
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-0/+5
* Add support for Intel SGX instructionsIlya Tocar2014-04-041-0/+3
* Update copyright yearsAlan Modra2014-03-051-2/+1
* Add support for CPUID PREFETCHWT1Ilya Tocar2014-02-211-0/+3
* Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar2014-02-121-0/+9
* Add Intel AVX-512 supportH.J. Lu2013-07-261-0/+91
* Support Intel SHAH.J. Lu2013-07-251-1/+4
* Support Intel MPXH.J. Lu2013-07-241-1/+11
* Implement Intel SMAP instructionsH.J. Lu2013-02-191-0/+3
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-201-0/+3
* Add AMD btver1 and btver2 supportH.J. Lu2012-08-171-1/+1
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-0/+9
* gas/Roland McGrath2012-06-221-3/+6
* Add HLEPrefixNone/HLEPrefixLock/HLEPrefixAny/HLEPrefixReleaseH.J. Lu2012-02-211-0/+4
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-0/+13
* Add vmfuncH.J. Lu2012-01-131-0/+3
* Add initial Intel K1OM support.H.J. Lu2011-07-221-0/+3
* Support AVX Programming Reference (June, 2011).H.J. Lu2011-06-101-3/+26
* Add support for TBM instructions.Quentin Neill2011-01-171-0/+3
* Implement BMI instructions.H.J. Lu2011-01-051-0/+3
* Add CheckRegSize to instructions which require register size check.H.J. Lu2010-10-141-0/+3
* Don't generate multi-byte NOPs for i686.H.J. Lu2010-08-061-0/+3
* Fix typos in comments in i386-opc.h.H.J. Lu2010-08-061-6/+6
* Fix a typo in comments for CpuFSGSBase.H.J. Lu2010-07-051-1/+1
* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-011-0/+12
* Update copyright.H.J. Lu2010-02-111-1/+1
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-02-111-0/+4
* Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu2010-01-241-2/+4